1. Field of the Invention
The invention relates in general to a nitride trapping memory device and method for reading the same, and more particularly to a method for dynamically adjusting read margin by using an extra cycling nitride trapping memory cell.
2. Description of the Related Art
Flash memory, a non-volatile semi-conductor memory element, is widely used many portable 3C products such as PDA, mobile phone, card reader, handy disc, and adaptor card due to the features of small volume, high capacity, low power consumption and re-writability.
Flash memory uses memory cell array to store logic data. Every memory cell includes a transistor having a gate electrode, a source electrode and a drain electrode. The gate electrode is coupled to a word line. A conventional memory cell uses the poly-silicon layer of the gate electrode to store the electrons. The poly-silicon layer is a conductive layer, which allows the electrons to move on poly-silicon layer freely. Therefore, every conventional memory cell can only store one bit of data. When reading the data stored in the conventional memory cell, the general practice is to apply a fixed read voltage onto the word line, so that the logic value stored therein is determined according to the current measured at the memory cell.
In order to achieve a high-density memory element, the Saifun Semiconductors Ltd. of Israel provides a nitride trapping memory cell. The nitride trapping memory cell is a memory allowing electrons to be erased or written into. The main difference between a nitride trapping memory cell and a conventional memory cell lies in that the nitride trapping memory cell uses a non-conductive nitride layer to store the electrons in the vicinity of the drain electrode and the source electrode. By doing so, every nitride trapping memory cell can store two bits of data, effectively increasing the density of the memory element.
However, if the area close to the drain electrode has already stored one bit of data, the second-bit effect will occur during the reverse read, causing the threshold voltage of forward read to rise up. Under such circumstance, the conventional method of applying a fixed read voltage to read the logic value stored in nitride trapping memory cell would reduce the reliability of the read data.
To resolve the above problem, the conventional method is to consider the second-bit effect in advance and pre-set a read ‘1’ margin. That is, before the memory element leaves the factory, the increase in threshold voltage value due to the second-bit effect is already considered and the estimated increase in threshold voltage is pre-set at a read ‘1’ margin, lest the reliability of the read data might be reduced due to the second-bit effect. However, such practice would increase the read voltage of the word line pre-set in the memory element, and increase read disturb effect in consequence.
Besides, a method of using two reference memory cells to read multi-bit flash memory and the device for making the same is disclosed. Each word line uses two reference memory cells respectively denoting that the word line has the distribution of the threshold voltages of high threshold voltage memory cells and the distribution of the threshold voltages of low threshold voltage memory cells. An average reference threshold voltage value can be obtained from the two reference memory cells. However, under practical operation, the threshold voltage of the two reference memory cells does not necessarily lie in the middle between the high threshold voltage distribution and the low threshold voltage distribution. Therefore, the read reference threshold voltage value obtained according to the above method is a read reference threshold voltage value obtained under ideal circumstances.
Moreover, U.S. Pat. No. 6,639,849 discloses a method which controls the threshold voltage value of the second reference memory cell according to the initial threshold voltage value of the first reference memory cell, so that the read reference threshold voltage value obtained from the first reference memory cell and the second reference memory cell can be assured to lie between the high threshold voltage distribution and the low threshold voltage distribution. However, complicated erasing routines and program verification routines are applied in the reference memory cell, not only increasing the difficulty in the design of circuits, but also increasing the read time.